1. Field of the Invention
The present invention relates to techniques for generating a layout for a transistor. More specifically, the present invention relates to a method and apparatus for generating a layout for a transistor so that a transistor which is fabricated from the layout achieves one or more desired operating characteristics.
2. Related Art
Nanometer-scale semiconductor fabrication technologies make it possible to fabricate a large number of transistors on an integrated circuit (IC) chip. As a result, the performance and functionality of IC chips has increased while the cost of individual transistors on the IC chips has decreased. However, nanometer-scale semiconductor fabrication technologies present a number of challenges to IC designers.
One problem is that the sizes of device features, which are presently being fabricated on IC chips are smaller than the wavelength of light used to expose the features on the IC chip. As a result, optical effects, such as interference and fringing, can cause the shape of a feature to be different than the intended shape of the feature. For example, FIG. 4 illustrates drawn layouts for transistor gate shapes and resulting fabricated transistor gate shapes. In FIG. 4, transistor gate 401 has a drawn gate length 402 and a drawn gate width 403, and transistor gate 406 has a drawn gate length 407 and a drawn gate width 408. (Note that an active diffusion region is located on either side of transistor gates 401 and 406.) Due to optical effects, a transistor fabricated based on the drawn transistor gate 401 may have a length 404 at the ends of the gate and a length 405 in the center of the gate. Similarly, a transistor fabricated from drawn transistor gate 406 may have a length 409 at the ends of the gate and a length 410 in the center of the gate. As illustrated, these optical effects create more pronounced variations on transistors with smaller feature sizes (e.g., smaller gate widths). For example, in the larger transistor in FIG. 4, lengths 404-405 may be substantially equal to each other and to drawn gate length 402, whereas in the smaller transistor, lengths 409-410 may be substantially different from each other and from drawn gate length 407.
These non-uniform fabricated transistor gate shapes can cause the transistor to exhibit undesirable operating characteristics such as current crowding, excessive leakage currents, and overheating. For example, the VTH versus W and ION versus W plots in FIG. 4 illustrate exemplary dependencies of the threshold voltage (VTH) to channel width (W) and the current (ION) to channel width (W) which can typically result from these optical effects.
One solution to this problem is to use Optical Proximity Correction (OPC) to adjust the drawn transistor gate shape so that a resulting transistor which is fabricated based on the adjusted transistor gate shape produces a substantially rectangular gate shape. Unfortunately, even if the fabricated transistor gate shape is substantially rectangular, transistors with smaller feature sizes tend to have a non-uniform threshold voltage distribution and a non-uniform current density across the transistor channel. As a result, the transistor's operating characteristics can be a non-linear function of channel width W, thereby complicating the task of designing circuits.
Hence, what is needed is a method and an apparatus for generating a layout for a transistor without the problems described above.